HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 26

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Table 1.1
Item
Ethernet controller
(EtherC)
Serial communi-
cation interface
with FIFO (SCIF),
2 channels
Note: * Magic Packet is a registered trademark of Advanced Micro Devices, Inc.
8
Features (cont)
Specifications
MAC (Media Access Control) functions
Compatible with MII (Media Independent Interface) standard
Magic Packet™* (with WOL (Wake On LAN) output)
Asynchronous mode
Synchronous mode
IrDA mode (conforming to IrDA 1.0)
Simultaneous transmission/reception (full-duplex) capability
Built-in dedicated baud rate generator allows selection of bit rate
Built-in 16-stage transmit and receive FIFOs enable high-speed,
continuous communication
Internal or external (SCK) transmit/receive clock source
Data frame assembly/disassembly (IEEE802.3-compliant frames)
CSMA/CD link management (collision avoidance, processing in case
CRC processing
Built-in FIFOs (512 bytes each for transmission and reception)
Supports full-duplex transmission/reception
Transmitting and receiving short and long packets
Converts 8-bit stream data from MAC level to MII nibble stream (4 bits)
Station management (STA) functions
18 TTL-level signals
Variable transfer rate: 10/100 Mbps
Data length: 7 or 8 bits
Stop bit length: 1 or 2
Parity: Even, odd, or none
Receive error detection: Parity errors, framing errors, overrun errors
Break detection
One serial communication format (8-bit data length)
Receive error detection: Overrun errors
Half-duplex communication used for IrDA communication
of collision)