HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 289

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 3—Refresh Control (RFSH): This bit determines whether or not the refresh operation of
DRAM/synchronous DRAM is performed
Bit 3: RFSH
0
1
Bit 2—Refresh Mode (RMODE): When the RFSH bit is 1, this bit selects normal refresh or self-
refresh. When the RFSH bit is 0, do not set this bit to 1. When the RFSH bit is 1, self-refresh
mode is entered immediately after the RMODE bit is set to 1. When the RFSH bit is 1 and this bit
is 0, a CAS-before-RAS refresh or auto-refresh is performed at the interval set in the 8-bit interval
timer. When a refresh request occurs during an external area access, the refresh is performed after
the access cycle is completed. When set for self-refresh, self-refresh mode is entered immediately
unless the chip is in the middle of a synchronous DRAM area access, in which case self-refresh
mode is entered when the access ends. Refresh requests from the interval timer are ignored during
self-refresh.
Bit 2: RMODE
0
1
7.2.8
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
272
Initial value:
Initial value:
Refresh Timer Control/Status Register (RTCSR)
R/W:
R/W:
Bit:
Bit:
Description
No refresh
Refresh
Description
Normal refresh
Self-refresh
CMF
R/W
15
—
0
R
7
0
CMIE
R/W
14
—
0
R
6
0
CKS2
R/W
13
—
0
R
5
0
CKS1
R/W
12
—
0
R
4
0
CKS0
R/W
11
—
0
R
3
0
RRC2
R/W
10
—
0
R
2
0
RRC1
R/W
—
9
0
R
1
0
(Initial value)
(Initial value)
RRC0
R/W
—
8
0
R
0
0