HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 210

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HD6417615

Manufacturer Part Number
HD6417615
Description
Hardware Manual
Manufacturer
Hitachi Semiconductor
Datasheet

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5.6
Signals on interrupt pins IRL3 to IRL0 pass through the noise canceler before being sent by the
interrupt controller to the CPU as interrupt requests, as shown in figure 5.10. The noise canceler
cancels noise that changes in short cycles. The CPU samples the interrupt requests between
executing instructions. During this period, the noise canceler output changes according to the
noise-eliminated pin level, so the pin level must be held until the CPU samples it. This means that
interrupt sources generally must not be cleared inside interrupt routines.
When an external vector is fetched, the interrupt source can also be cleared when the external
vector fetch cycle is detected.
192
IRL3–IRL0
pin level
Noise canceler
output
Interrupt request
to CPU
Interrupt acceptance
signal from CPU
1111
Sampling of Pins IRL3–IRL0
IRL0
IRL1
IRL2
IRL3
1111
1011 for
1 clock
due to
noise
1111
canceler
Figure 5.10 IRL3–IRL0 Pin Sampling
Noise
Cleared when interrupt is accepted
1101
controller
Interrupt
Level 2 interrupt
1101
accepted
Interrupt
Interrupt
request
CPU
Level 6 interrupt
1001
1001

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