HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 174

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HD6417615

Manufacturer Part Number
HD6417615
Description
Hardware Manual
Manufacturer
Hitachi Semiconductor
Datasheet

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Table 5.4 (b) Interrupt Exception Vectors and Priority Order (IRQ Mode) (cont)
Interrupt Source
SIO0
SIO1
SIO2
Reserved
Notes: 1. An external vector number fetch can be performed without using the auto-vector
156
2. Vector numbers are set in the on-chip vector number register.
3. REF is the refresh control unit within the bus state controller.
4. Set to IRL1–IRL15 or IRQ0–IRQ3 by the EXIMD bit in ICR.
5. In the SH7615, VCRB (14–0) is a reserved register and must not be accessed.
6. The E-DMAC interrupt (EINT) is the OR of those of the 19 interrupt sources in the
RERI0
TERI0
RDFI0
TDEI0
RERI1
TERI1
RDFI1
TDEI1
RERI2
TERI2
RDFI2
TDEI2
numbers shown in this table. The external vector numbers are 0–127.
EtherC/E-DMAC status register (EESR) that are enabled by the EtherC/E-DMAC status
interrupt permission register (EESIPR). As the three status bits in the EtherC status
register (ECSR) can be copied into the ECI bit in EESR as an interrupt source, EINT is
input to the INTC as the OR of a maximum of 21 interrupt sources.
Vector
No.
0–127*
0–127*
0–127*
0–127*
0–127*
0–127*
0–127*
0–127*
0–127*
0–127*
0–127*
0–127*
128–255 —
Vectors
2
2
2
2
2
2
2
2
2
2
2
2
Vector
Table
Address
VBR +
(vector No.
4)
Interrupt
Priority
Order
(Initial
Value)
15–0 (0)
15–0 (0)
15–0 (0)
IPR (Bit
Numbers)
IPRE
(11–8)
IPRE
(7–4)
IPRE
(3–0)
Priority
within
IPR
Setting
Unit
High
Low
High
Low
High
Low
VCR (Bit
Numbers)
VCRP (14–8) High
VCRP (6–0)
VCRQ (14–8)
VCRQ (6–0)
VCRR (14–8)
VCRR (6–0)
VCRS (14–8)
VCRS (6–0)
VCRT (14–8)
VCRT (6–0)
VCRU (14–8)
VCRU (6–0)
Default
Priority
Low

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