HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 550

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

13.2.2
The watchdog timer control/status register (WTCSR) is an 8-bit read/write register. The method of
writing to WTCSR differs from that of most other registers to prevent inadvertent rewriting. See
section 13.2.4, Notes on Register Access, for details. Its functions include selecting the timer
mode and clock source. Bits 7 to 5 are initialized to 000 by a reset, in standby mode, when the
clock frequency is changed, and in clock pause mode. Bits 2 to 0 are initialized to 000 by a reset,
but are not initialized in standby mode, when the clock frequency is changed, or in clock pause
mode.
Bit 7—Overflow Flag (OVF): Indicates that WTCNT has overflowed from H'FF to H'00 in
interval timer mode. It is not set in watchdog timer mode.
Bit 7: OVF
0
1
Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or
interval timer. When WTCNT overflows, the WDT either generates an interval timer interrupt
(ITI) or generates a WDTOVF signal, depending on the mode selected.
Bit 6: WT/IT
0
1
536
Initial value:
Watchdog Timer Control/Status Register (WTCSR)
R/W:
Bit:
R/(W)*
OVF
7
0
Description
No overflow of WTCNT in interval timer mode
Cleared by reading OVF, then writing 0 in OVF
WTCNT overflow in interval timer mode
Description
Interval timer mode: interval timer interrupt (ITI) request to the CPU
when WTCNT overflows
Watchdog timer mode: WDTOVF signal output externally when WTCNT
overflows. Section 13.2.3, Reset Control/Status Register (RSTCSR),
describes in detail what happens when WTCNT overflows in watchdog
timer mode
WT/IT
R/W
6
0
TME
R/W
5
0
—
—
4
1
—
—
3
1
CKS2
R/W
2
0
CKS1
R/W
1
0
(Initial value)
(Initial value)
CKS0
R/W
0
0