HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 660

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

The TCR registers are 8-bit registers that control the TCNT channels. The TPU has three TCR
registers, one for each of channels 0 to 2. The TCR registers are initialized to H'00 by a reset.
TCNT operation should be stopped when making TCR settings.
Bits 7, 6, and 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the
TCNT counter clearing source.
Channel
0
Channel
1, 2
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
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2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
3. Bit 7 is reserved in channels 1and 2. It is always read as 0. The write value should
buffer register setting has priority, and compare match/input capture does not occur.
always be 0.
Bit 7:
CCLR2
0
1
Bit 7:
Reserved*
0
3
Bit 6:
CCLR1
0
1
0
1
Bit 6:
CCLR1
0
1
Bit 5:
CCLR0
0
1
0
1
0
1
0
1
Bit 5:
CCLR0
0
1
0
1
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous
clearing/synchronous operation *
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
capture *
TCNT cleared by TGRD compare match/input
capture *
TCNT cleared by counter clearing for another
channel performing synchronous
clearing/synchronous operation *
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *
2
2
1
1
1
(Initial value)
(Initial value)