HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 499

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Refreshes cannot be performed during a burst transfer, so ensure that the number of transfers
satisfies the refresh request period when a memory requiring refreshing is used. When the transfer
request source is an external request (DREQ) in burst mode, set the DS bit of CHCR0 and CHCR1
to 1 (edge detection). If the DS bits of CHCR0 and CHCR1 are set to 0 (level detection), operation
is not guaranteed.
484
Figure 11.11 DMA Transfer Timing in Burst Mode (Single Address, DREQ Falling-Edge
Burst Mode
In burst mode, once the DMAC gets the bus, the transfer continues until the transfer end
condition is satisfied. When external request mode is used with level detection of the DREQ
pin, however, negating DREQ will pass the bus to the other bus master after completion of the
bus cycle of the DMAC that currently has an acknowledged request, even if the transfer end
conditions have not been satisfied. When the transfer request source is an on-chip peripheral
module, however, cycle-steal mode is always used.
Figure 11.11 shows an example of DMA transfer timing in burst mode. The transfer conditions
for the example in the figure are as shown below.
• Single address mode
• DREQ level detection
DREQ
cycle
Bus
CPU
CPU
CPU
DMAC DMAC DMAC DMAC
Detection)
CPU
CPU
CPU