HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 450

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bits 4 to 0—Rx FIFO Depth (RFD): Specifies either 256 or 512 bytes as the depth (size) of the
receive FIFO (which has a maximum capacity of 512 bytes). The actual FIFO depth is 256 times
the set value. The setting cannot be changed after transmission/reception has started.
Bits 4 to 0:
RFD
0
1
10.2.12 Receiver Control Register (RCR)
RCR specifies the control method for the RE bit in ECMR when a frame is received.
Note: When setting this register, do so in the receiving-halt state.
Bits 31 to 1—Reserved: These bits should only be written with 0.
Bit 0—Receive Enable Control (RNC)
Bit 0: RNC
0
1
Note: * This setting is normally used for continuous frame reception.
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Description
256 bytes
512 bytes
Description
When reception of one frame is completed, the E-DMAC writes the receive
status into the descriptor and clears the RR bit in EDRRR
When reception of one frame is completed, the E-DMAC writes the receive
status into the descriptor, reads the next descriptor, and prepares to receive
the next frame*
31
—
—
—
—
0
7
0
30
—
—
—
—
0
6
0
29
—
—
—
—
0
5
0
. . .
. . .
. . .
. . .
—
—
4
0
11
—
—
—
—
0
3
0
10
—
—
—
—
0
2
0
—
—
—
—
9
0
1
0
(Initial value)
(Initial value)
RNC
R/W
—
—
8
0
0
0
435