HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 262

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

CPU Data Access Cycle Break Condition Settings
244
Register settings: BARA = H'00123456 / BAMRA = H'00000000 / BBRA = H'0064
Set conditions:
On channel A, a user break interrupt is generated by a longword read at address H'00123454, a
word read at address H'00123456, or a byte read at address H'00123456.
On channel B, a user break interrupt is generated by a word read at address H'01000000.
On channel C, a user break interrupt is generated when H'A512 is written by word access to an
address from H'000ABC00 to H'000ABCFE.
On channel D, a user break interrupt is generated when H'4567 is written by word access to
address H'1001E000 in Y memory space.
BARB = H'01000000 / BAMRB = H'00000000 / BBRB = H'0066
BARC = H'000ABCDE / BAMRC = H'000000FF / BBRC = H'006A
BDRC = H'0000A512 / BDMRC = H'00000000
BARD = H'1001E000 / BAMRD = H'FFFF0000 / BBRD = H'036A
BDRD = H'00004567 / BDMRD = H'00000000
BRCR = H'00000808
All channels independent
Channel A: Address:
Channel B: Address:
Channel C: Address: H'000ABCDE; address mask: H'00000000
Channel D: Y address: H'1001E000; address mask: H'FFFF0000
Bus cycle: CPU, data access, read (operand size not included
Bus cycle: CPU, data access, read, word
Data:
Bus cycle: CPU, data access, write, word
Data:
Bus cycle: CPU, data access, write, word
H'00123456; address mask: H'00000000
in conditions)
H'01000000; address mask: H'00000000
H'0000A512; data mask: H'00000000
H'00004567; data mask: H'00000000