HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 143

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

4.1.2
Exception handling sources are detected, and exception handling started, according to the timing
shown in table 4.2.
Table 4.2
Exception Source
Reset
Address error
Interrupts
Instructions
When exception handling starts, the CPU operates as follows:
1. Exception handling triggered by reset
2. Exception handling triggered by address errors, interrupts, and instructions
The initial values of the program counter (PC) and stack pointer (SP) are fetched from the
exception vector table (PC and SP are respectively addresses H'00000000 and H'00000004 for
a power-on reset and addresses H'00000008 and H'0000000C addresses for a manual reset).
See section 4.1.3, Exception Vector Table, for more information. 0 is then written to the vector
base register (VBR) and 1111 is written to the interrupt mask bits (I3–I0) of the status register
(SR). The program begins running from the PC address fetched from the exception vector
table.
SR and PC are saved to the stack address indicated by R15. For interrupt exception handling,
the interrupt priority level is written to the SR’s interrupt mask bits (I3–I0). For address error
and instruction exception handling, the I3–I0 bits are not affected. The start address is then
fetched from the exception vector table and the program begins running from that address.
Exception Handling Operations
Timing of Exception Source Detection and Start of Exception Handling
Power-on reset
Manual reset
Trap instruction
General illegal
instructions
Illegal slot
instructions
Timing of Source Detection and Start of Handling
Starts when the NMI pin is high and the RES pin changes from
low to high
Starts when the NMI pin is low and the RES pin changes from
low to high
Detected when instruction is decoded and starts when the
previous executing instruction finishes executing
Detected when instruction is decoded and starts when the
previous executing instruction finishes executing
Starts from the execution of a TRAPA instruction
Starts from the decoding of undefined code anytime except after
a delayed branch instruction (delay slot)
Starts from the decoding of undefined code placed directly
following a delayed branch instruction (delay slot) or of an
instruction that rewrites the PC
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