HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 517

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Transfer Width
Transfer bus mode
Transfer address mode
Transfer Width
Transfer bus mode
Transfer address mode
Note: * Do not set a 16-byte unit; operation is not guaranteed if this setting is made.
502
Note: * n is the nth 16-byte transfer.
Figure 11.37 DREQn Pin Input Detection Timing in Cycle-Steal Mode with Edge Detection
Cycle-Steal Mode Edge Detection—16-Bit Transfer
With 16-byte transfer, the first request signal is the first transfer request, and the second
transfer request is accepted when the next request signal is accepted. The third and fourth
requests are accepted in the same way.
Cycle-Steal Mode Level Detection
In level detection mode, too, a request cannot be canceled once accepted.
(Active high)
(Active high)
Bus cycle
DREQn
DACKn
Clock
16-Byte Transfer
Cycle-steal mode
Dual/single mode
Byte/Word/Longword*
Cycle-steal mode
Dual/single mode
1st
acceptance
CPU
Blind zone
(16-Byte Transfer Setting)
CPU
2nd
acceptance
DACK*1 DACK*2 DACK*3 DACK*4
DMAC*1 DMAC*2 DMAC*3 DMAC*4
DREQn Detection
Method
DACKn output timing
Bus cycle
DREQn Detection
Method
DACKn output timing
Bus cycle
Edge Detection
Read DACK/write
DACK
Basic bus cycle
Level Detection
Read DACK/write
DACK
Basic bus cycle
DMA