HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 551

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 5—Timer Enable (TME): Enables or disables the timer.
Bit 5: TME
0
1
Bits 4 and 3—Reserved: These bits are always read as 1. The write value should always be 1.
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources for input to WTCNT. The clock signals are obtained by dividing the frequency of the
system clock ( ).
Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source
0
1
Note: * The overflow interval listed is the time from when the WTCNT begins counting at H'00 until
13.2.3
Note: * Only 0 can be written in bit 7, to clear the flag.
RSTCSR is an 8-bit read/write register that controls output of the reset signal generated by
watchdog timer counter (WTCNT) overflow and selects the internal reset signal type. The method
of writing to RSTCSR differs from that of most other registers to prevent inadvertent rewriting.
See section 13.2.4, Notes on Register Access, for details. RSTCR is initialized to H'1F by input of
Initial value:
an overflow occurs.
Reset Control/Status Register (RSTCSR)
R/W:
0
1
0
1
Bit:
WOVF
R/(W)*
7
0
Description
Timer disabled: WTCNT is initialized to H'00 and count-up stops
Timer enabled: WTCNT starts counting. A WDTOVF signal or interrupt
is generated when WTCNT overflows
0
1
0
1
0
1
0
1
RSTE
R/W
6
0
RSTS
/4 (Initial value)
/128
/256
/512
/1024
/2048
/8192
/16384
R/W
5
0
—
4
1
R
Overflow Interval* ( = 60 MHz)
17.0 µs
544 µs
1.1 ms
2.2 ms
4.4 ms
8.7 ms
34.8 ms
69.6 ms
—
Description
3
1
R
—
2
1
R
—
1
1
R
(Initial value)
—
0
1
R
537