HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 598

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Clock: Either an internal clock generated by the built-in baud rate generator or an external clock
input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A
bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details of SCIF clock source
selection, see table 14.9.
When an external clock is input at the SCK pin, the input clock frequency should be 16, 8, or 4
times the bit rate used.
When the SCIF is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is 16, 8, or 4 times the bit rate.
Data Transmit/Receive Operations
SCIF Initialization (Asynchronous Mode)
Before transmitting and receiving data, it is necessary to clear the TE and RE bits to 0 in
SCSCR, then initialize the SCIF as described below.
When the operating mode, communication format, etc., is changed, the TE and RE bits must be
cleared to 0 before making the change using the following procedure. When the TE bit is
cleared to 0, the transmit shift register (SCTSR) is initialized. Note that clearing the TE and RE
bits to 0 does not change the contents of the serial status 1 register (SC1SSR), the transmit
FIFO data register (SCFTDR), or the receive FIFO data register (SCFRDR). The TE bit should
not be cleared to 0 until all transmit data has been transmitted and the TEND flag has been set
in SC1SSR. It is possible to clear the TE bit to 0 during transmission, but the data being
transmitted will go to the high-impedance state after TE is cleared. Also, before starting
transmission by setting TE again, the TFRST bit should first be set to 1 in SCFCR to reset
SCFTDR.
When an external clock is used the clock should not be stopped during operation, including
initialization, since operation will be unreliable in this case.
Figure 14.4 shows a sample SCIF initialization flowchart.
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