HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 380

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Table 8.3
Way 0
Way 1
Way 2
Way 3
Note: —: Holds the value before update.
Table 8.4
Way 0
Way 1
Way 2
Way 3
Note: —: Don’t care.
8.4.6
Purges of the entire cache area can only be carried out by writing 1 to the CP bit in CCR. Writing
1 to the CP bit initializes the valid bit of the address array, and all bits of the LRU information, to
0. Cache purges are completed in 1 cycle, but additional time is required for writing to CCR.
Always initialize the valid bit and LRU before enabling the cache.
When the cache is enabled, instructions are read from the cache even during writing to CCR. This
means that the prefetched instructions are read from the cache. To do a proper purge, write 0 to
CCR’s CE bit, then disable the cache and purge. Since CCR’s CE bit is cleared to 0 by a power-on
reset or manual reset, the cache can be purged immediately by a reset.
8.4.7
Associative purges invalidate 1 line (16 bytes) corresponding to specific address contents when
the contents are in the cache.
When the contents of a shared address are rewritten by one CPU in a multiprocessor configuration
or a configuration in which the chip's internal E-DMAC (or DMAC) and CPU share memory, that
address must be invalidated in the cache of the other CPU if it is present there.
When writing to or reading the address obtained by adding H'40000000 to the address to be
purged, the valid bit of the entry storing the address prior to addition are initialized to 0.
364
Cache Initialization
Associative Purges
LRU Information after Update
Selection Conditions for Replaced Way
Bit 5
0
1
—
—
Bit 5
1
0
—
—
Bit 4
0
—
1
—
Bit 4
1
—
0
—
Bit 3
0
—
—
1
Bit 3
1
—
—
0
Bit 2
—
0
1
—
Bit 2
—
1
0
—
Bit 1
—
0
—
1
Bit 1
—
1
—
0
Bit 0
—
—
0
1
Bit 0
—
—
1
0