HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 241

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

6.2.17
Break bus cycle register D (BBRD) is a 16-bit readable/writable register that sets five channel D
break conditions: (1) internal bus (C-bus, I-bus)/X memory bus/Y memory bus), (2) CPU
cycle/on-chip DMAC (DMAC, E-DMAC) cycle, (3) instruction fetch/data access, (4) read/write,
and (5) operand size. BBRD is initialized to H'0000 by a power-on reset; after a manual reset, its
value is undefined.
Bits 15 to 10—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 9—X/Y Memory Bus Enable D (XYED): Selects whether the X/Y bus is used as a channel D
break condition.
Bit 9: XYED
0
1
Bit 8—X Bus/Y Bus Select D (XYSD): Selects whether the X bus or the Y bus is used as a
channel D break condition. This bit is valid only when bit XYED = 1.
Bit 8: XYSD
0
1
The configuration of bits 7 to 0 is the same as for BBRA.
Initial value:
Initial value:
Break Bus Cycle Register D (BBRD)
R/W:
R/W:
Bit:
Bit:
Description
Cache bus or internal bus is selected as condition for channel D address/data
X/Y bus is selected as condition for channel D address/data
Description
X bus is selected as channel D break condition
Y bus is selected as channel D break condition
CPD1
R/W
15
—
0
R
7
0
CPD0
R/W
14
—
0
R
6
0
IDD1
R/W
13
—
0
R
5
0
IDD0
R/W
12
—
0
R
4
0
RWD1
R/W
11
—
0
R
3
0
RWD0
R/W
10
—
0
R
2
0
XYED
SZD1
R/W
R/W
9
0
1
0
(Initial value)
(Initial value)
XYSD
SZD0
R/W
R/W
8
0
0
0
223