HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 569

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor
format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only
valid in asynchronous mode; it is invalid in synchronous mode and IrDA mode.
For details of the multiprocessor communication function, see section 14.3.3, Multiprocessor
Communication Function.
Bit 2: MP
0
1
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the built-
in baud rate generator. The clock source can be selected from P , P /4, P /16, and P /64,
according to the setting of bits CKS1 and CKS0.
For the relationship between the clock source, the bit rate register setting, and the baud rate, see
section 14.2.9, Bit Rate Register (SCBRR).
Bit 1:
CKS1
0
1
Note: P = peripheral clock
14.2.6
The serial control register (SCSCR) performs enabling or disabling of SCIF transmit/receive
operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the
transmit/receive clock source.
SCSCR can be read or written to by the CPU at all times.
SCSCR is initialized to H'00 by a reset, by the module standby function, and in standby mode.
556
Initial value:
Serial Control Register (SCSCR)
Bit 0:
CKS0
0
1
0
1
R/W:
Bit:
Description
Multiprocessor function disabled
Multiprocessor format selected
R/W
TIE
Description
P clock
P /4 clock
P /16 clock
P /64 clock
7
0
R/W
RIE
6
0
R/W
TE
5
0
R/W
RE
4
0
MPIE
R/W
3
0
—
2
0
R
CKE1
R/W
1
0
(Initial value)
(Initial value)
CKE0
R/W
0
0