HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 351

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

the clock is selected by CKS2–CKS0, RTCNT starts counting up from the value at that time. The
RTCNT value is constantly compared with the RTCOR value, and when the two values match, a
refresh request is generated and the number of CAS-before-RAS refreshes set in bits RRC2–RRC0
are performed. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure
7.48 shows the CAS-before-RAS refresh cycle timing.
The number of RAS assert cycles in the refresh cycle is specified by bits TRAS1 and TRAS0 in
MCR. As with ordinary accesses, the specification of the RAS precharge time in the refresh cycle
follows the setting of bits TRP1 and TRP0 in MCR.
Self-Refreshing: A self-refresh is started by setting both the RMODE bit and the RFSH bit to 1.
During the self-refresh, DRAM cannot be accessed. Self-refreshing is cleared by clearing the
RMODE bit to 0. Self-refresh timing is shown in figure 7.49. Settings must be made so that self-
refresh clearing and data retention are performed correctly, and CAS-before-RAS refreshing is
immediately performed at the correct intervals. When self-refreshing is started from the state in
which CAS-before-RAS refreshing is set, or when exiting standby mode by means of a manual
reset or NMI, auto-refreshing is restarted if RFSH is set to 1 and RMODE is cleared to 0 when
self-refresh mode is cleared. If the transition from clearing of self-refresh mode to starting auto-
refresh takes time, this time should be taken into consideration when setting the initial value of
RTCNT. When the RTCNT value is set to RTCOR-1, the refresh can be started immediately.
After self-refreshing has been set, the self-refresh state continues even if the chip standby state is
entered using the chip’s standby function. The self-refresh state is also maintained even after
recovery from standby mode by means of NMI input.
334
CKIO
RAS
CASn
RD/WR
RD
Figure 7.48 DRAM CAS-before-RAS Refresh Cycle Timing
Tp
Trr
Trc1
Trc2
Tre