HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 339

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

7.6.3
The basic timing of a DRAM access is 3 cycles. Figure 7.37 shows the basic DRAM access
timing. Tp is the precharge cycle, Tr is the RAS assert cycle, Tc1 is the CAS assert cycle, and Tc2
is the read data fetch cycle. When accesses are consecutive, the Tp cycle of the next access
overlaps the Tc2 cycle of the previous access, so accesses can be performed in a minimum of 3
cycles each.
322
Read
Write
Basic Timing
Note: * DACKn waveform when active-low is specified.
CKIO
A24–A16
A15–A1
RAS
CASn
RD/WR
RD
D31–D0
RD/WR
RD
D31–D0
DACKn*
Figure 7.37 Basic Access Timing
Tp
Tr
Tc1
Tc2