HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 528

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

12.2.3
ICR is a 16-bit read-only register. When a rising edge or falling edge of the input capture signal
(FTI pin) is detected, the current FRC value is transferred to ICR. At the same time, the input
capture flag (ICF) in FTCSR is set to 1. The edge of the input signal can be selected using the
input edge select bit (IEDG) in TCR.
Because ICR is a 16-bit register, data transfers involving the CPU are performed via a temporary
register (TEMP). See Section 12.3, CPU Interface, for more detailed information. To ensure that
the input capture operation is reliably performed, set the pulse width of the input capture input
signal to six system clocks ( ) or more.
ICR is initialized to H'0000 by a reset, in standby mode, and when the module standby function is
used.
12.2.4
TIER is an 8-bit read/write register that controls enabling of all interrupt requests. TIER is
initialized to H'01 by a reset, in standby mode, and when the module standby function is used.
Bit 7—Input Capture Interrupt Enable (ICIE): Selects enabling/disabling of the ICI interrupt
request when the input capture flag (ICF) in FTCSR is set to 1.
Bit 7: ICIE
0
1
Bits 6 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Initial value:
Initial value:
Input Capture Register (FICR)
Timer Interrupt Enable Register (TIER)
R/W:
R/W:
Bit:
Bit:
ICIE
R/W
15
0
R
7
0
Description
Interrupt request (ICI) caused by ICF disabled
Interrupt request (ICI) caused by ICF enabled
14
—
0
R
6
0
R
13
—
0
R
5
0
R
…
…
…
…
—
4
0
R
OCIAE
R/W
3
0
R
3
0
OCIBE
R/W
2
0
R
2
0
OVIE
R/W
1
0
R
1
0
(Initial value)
—
0
0
R
0
1
R
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