HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 714

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

16.7
Note that the kinds of operation and contention described below occur during TPU operation.
Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of
single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not
operate properly with a narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 16.44 shows the input clock
conditions in phase counting mode.
702
P
Address
Status flag
Interrupt
request
signal
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Figure 16.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Notes: Phase difference and overlap : 1.5 states or more
Usage Notes
Pulse width
Figure 16.43 Timing for Status Flag Clearing by DMAC Activation
Overlap
Pulse width
Phase
differ-
ence
Overlap
: 2.5 states or more
Phase
differ-
ence
Pulse width
Source address
T1
read cycle
DMAC
T2
Pulse width
T1
write cycle
Destination
address
DMAC
T2
Pulse width