HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 247

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 12—Reserved: This bit is always read as 0. The write value should always be 0.
Bit 11—Data Break Enable C (DBEC): Selects whether a data bus condition is to be included in
the channel C break conditions.
Bit 11: DBEC
0
1
Bit 10—PC Break Select C (PCBC): Selects whether a channel C instruction fetch cycle break is
effected before or after execution of the instruction.
Bit 10: PCBC
0
1
Bits 9 and 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—CPU Condition Match Flag D (CMFCD): This flag is set to 1 when a CPU bus cycle
condition, among the break conditions set for channel D, is satisfied. This flag is not cleared to 0
(if the flag setting is to be checked again after it has once been set, the flag must be cleared by a
write).
Bit 7: CMFCD
0
1
Bit 6—DMAC Condition Match Flag D (CMFPD): This flag is set to 1 when a DMAC bus cycle
condition, among the break conditions set for channel D, is satisfied. This flag is not cleared to 0
(if the flag setting is to be checked again after it has once been set, the flag must be cleared by a
write).
Bit 6: CMFPD
0
1
Description
Data bus condition is not included in channel C conditions
Data bus condition is included in channel C conditions
Description
Channel C instruction fetch cycle break is effected before instruction execution
Channel C instruction fetch cycle break is effected after instruction execution
Description
User break interrupt has not been generated by a channel D CPU cycle
condition
User break interrupt has been generated by a channel D CPU cycle condition
Description
User break interrupt has not been generated by a channel D on-chip DMAC
cycle condition
User break interrupt has been generated by a channel D on-chip DMAC cycle
condition
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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