HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 612

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

No
No
No
Read ER, BRK, FER, and DR bits in
SC1SSR, and ORER bit in SC2SSR
Read BRK and DR bits in SC1SSR,
and clear RDF flag to 0 in SC1SSR
Read receive data from SCFRDR,
Read receive data from SCFRDR
Figure 14.14 Sample Multiprocessor Serial Reception Flowchart (1)
Set MPIE bit to 1 in SCSCR
Clear RE bit to 0 in SCSCR
Read RDF flag in SC1SSR
Read RDF flag in SC1SSR
and ER bit in SC2SSR
BRK
All data received?
BRK
Start of reception
This station’s ID?
End of reception
Initialization
ORER = 1?
RDF = 1?
RDF = 1?
Yes
DR
DR
No
Yes
Yes
Yes
No
ER = 1?
ER
Yes
Yes
No
1
2
3
4
Error handling
5
1. PFC initialization: Set the RxD pin,
2. ID reception cycle: Set the MPIE bit to
3. SCIF status check, ID reception and
4. Receive error handling and break
5. SCIF status check and receive data
and the SCK pin if necessary, with
the PFC.
1 in SCSCR.
comparison: Read SC1SSR and
check that the RDF bit is set to 1,
then read the receive data in the
receive FIFO data register (SCFRDR)
and compare it with this station’s ID.
If the data is not this station’s ID, set
the MPIE bit to 1 again, and clear the
RDF bit to 0.
If the data is this station’s ID, clear
the RDF bit to 0.
detection: Read the ER, BRK, FER,
and DR flags in SC1SSR and the
ORER flag in SC2SSR to check
whether a receive error has occurred.
If a receive error has occurred, read
the ER, BRK, FER, and DR flags in
SC1SSR and the ORER flag in
SC2SSR to identify the error. After
performing the appropriate error
handling, ensure that ER, BRK, DR,
and ORER are all cleared to 0. The
setting of the EI bit in SC2SSR
determines whether reception is
continued or halted when the ORER
bit is set to 1. In the case of a framing
error, a break can be detected by
reading the value of the RxD pin.
read: Read the serial status 1 register
(SC1SSR) and check that RDF = 1,
then read receive data from the
receive FIFO data register
(SCFRDR).
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