HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 589

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 5: TTRG1
0
1
Note: * Initial value. Figures in parentheses are the number of empty bytes in SCFTDR when the
Bit 3—Modem Control Enable (MCE): Enables or disables the CTS and RTS modem control
signals.
Bit 3: MCE
0
1
Note: * CTS is fixed at active-0 regardless of the input value, and RTS output is also fixed at 0.
Bit 2—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the transmit
FIFO data register and resets it to the empty state.
Bit 2: TFRST
0
1
Note: A reset operation is performed in the event of a reset, module standby, or in standby mode.
Bit 1—Receive FIFO Data Register Reset (RFRST): Invalidates the receive data in the receive
FIFO data register and resets it to the empty state.
Bit 1: RFRST
0
1
Note: A reset operation is performed in the event of a reset, module standby, or in standby mode.
Bit 0—Loopback Test (LOOP): Internally connects the transmit output pin (TxD) and receive
input pin (RxD), enabling loopback testing.
Bit 0: LOOP
0
1
576
flag is set.
Bit 4: TTRG0
0
1
0
1
Description
Modem signals disabled*
Modem signals enabled
Description
Reset operation disabled
Reset operation enabled
Description
Reset operation disabled
Reset operation enabled
Description
Loopback test disabled
Loopback test enabled
Transmit Trigger Number
8 (8)*
4 (12)
2 (14)
1 (15)
(Initial value)
(Initial value)
(Initial value)
(Initial value)