HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 506

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Acknowledge Signal Output when External Memory Is Set as Synchronous DRAM: When
external memory is set as synchronous DRAM, DACK output becomes valid simultaneously with
the start of the DMA address, and becomes invalid when the address output ends.
When external memory is set as synchronous DRAM auto-precharge and AM = 0, the
acknowledge signal is output across the row address, read command, wait and read address of the
DMAC read (figure 11.19). Since the synchronous DRAM read has only burst mode, during a
single read an invalid address is output; the acknowledge signal, however, is output on the same
timing (figure 11.20). At this time, the acknowledge signal is extended until the write address is
output after the invalid read. A synchronous DRAM burst read is performed in the case of 16-byte
transfer. As 16-byte transfer is enabled only in auto-request mode and in external request mode
with edge detection, when using on-chip peripheral module requests or external request mode with
level detection, byte, word, or longword should be set as the transfer unit. Operation is not
guaranteed if a 16-byte unit is set when using on-chip peripheral module requests or external
request mode with level detection. When AM = 1, the acknowledge signal is output across the row
address and column address of the DMAC write (figure 11.21).
Clock
DACKn
Read
(Active high)
command
Row
address
Address
Read 1
Read 2
Read 3
Read 4
CPU
bus
DMAC read (basic timing)
Figure 11.19 DACKn Output in Synchronous DRAM Burst Read
(Auto-Precharge, AM = 0)
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