HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 179

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

5.3.5
Interrupt priority level setting register E (IPRE) is a 16-bit read/write register that sets the priority
levels (0–15) of on-chip peripheral module interrupts. IPRE is initialized to H'0000 by a reset. It is
not initialized in standby mode.
Bits 15 to 12—Serial Communication Interface with FIFO 2 (SCIF2) Interrupt Priority Level 3 to
0 (SCF2IP3–SCF2IP0): These bits set the serial communication interface with FIFO 2 (SCIF2)
interrupt priority level. There are four bits, so the value can be set between 0 and 15.
Bits 11 to 0—Serial I/O 0 to 2 (SIO0–SIO2) Interrupt Priority Level 3 to 0 (SIOnIP3–SIOnIP0, n
= 0–2): These bits set the serial I/O 0 to 2 (SIO0–SIO2) interrupt priority levels. There are four
bits for each interrupt, so the value can be set between 0 and 15.
Table 5.5 shows the relationship between on-chip peripheral module interrupts and interrupt
priority level setting registers.
Table 5.5
Register
Interrupt priority level setting
register A
Interrupt priority level setting
register B
Interrupt priority level setting
register C
Interrupt priority level setting
register D
Interrupt priority level setting
register E
Initial value:
Initial value:
Interrupt Priority Level Setting Register E (IPRE)
Interrupt Request Sources and IPRA–IPRE
R/W:
R/W:
Bit:
Bit:
SCF2IP3 SCF2IP2 SCF2IP1 SCF2IP0 SIO0IP3 SIO0IP2 SIO0IP1 SIO0IP0
SIO1IP3 SIO1IP2 SIO1IP1 SIO1IP0 SIO2IP3 SIO2IP2 SIO2IP1 SIO2IP0
R/W
R/W
15
0
7
0
R/W
R/W
14
Bits 15 to 12
Reserved
E-DMAC
IRQ0
TPU0
SCIF2
0
6
0
R/W
R/W
13
0
5
0
Bits 11 to 8
DMAC0,
DMAC1
FRT
IRQ1
TPU1
SIO0
R/W
R/W
12
0
4
0
R/W
R/W
11
0
3
0
Bits 7 to 4
WDT, REF
Reserved
IRQ2
TPU2
SIO1
R/W
R/W
10
0
2
0
R/W
R/W
Bits 3 to 0
Reserved
Reserved
IRQ3
SCIF1
SIO2
9
0
1
0
R/W
R/W
8
0
0
0
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