HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 125

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

3.2.2
Table 3.2 lists the functions and operation of clock modes 0 to 6.
Table 3.2
Clock Mode
0
1
2
3
4
Clock Operating Mode Settings
Operating Modes
Function/Operation
PLL circuits 1 and 2 operate. A clock is output with the same
phase (with the same frequency as Eø) as the internal clocks
(Iø, Eø, Pø) from the CKIO pin
PLL circuits 1 and 2 can be switched between the operating
and halted states by means of control bits in the frequency
modification register (FMR). The CKIO pin can also be placed
in the high-impedance state
Normally, mode 0 should be used.
PLL circuits 1 and 2 operate. A clock (with the same
frequency as Eø) 1/4 ø cycle in advance of the chip's internal
system clock ø is output from the CKIO pin.
PLL circuits 1 and 2 can be switched between the operating
and halted states by means of control bits in the frequency
modification register (FMR). The CKIO pin can also be placed
in the high-impedance state. However, clock phase shifting is
not performed when PLL circuit 1 is halted.
Normally, mode 0 should be used.
Only PLL circuit 2 operates. The clock from PLL circuit 2 is
output from the CKIO pin (having the same frequency as the
Eø). As PLL circuit 1 does not operate, phases are not
matched in this mode
PLL circuit 2 can be switched between the operating and
halted states by means of a control bit in the frequency
modification register (FMR). The CKIO pin can also be placed
in the high-impedance state
Only PLL circuit 2 operates. The CKIO pin is high-impedance
PLL circuit 2 can be switched between the operating and
halted states by means of a control bit in the frequency
modification register (FMR)
Only PLL circuit 1 operates. Operate PLL circuit 1 when
operating with synchronization of the phases of the clock
input from the CKIO pin and the internal clocks (Iø, Eø, Pø).
PLL circuit 2 does not operate in this mode
PLL circuit 1 can be switched between the operating and
halted states by means of a control bit in the frequency
modification register (FMR)
Clock Source
Crystal resonator/
external clock input
External clock input
107