HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 14

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

13.2 Register Descriptions ......................................................................................................... 535
13.3 Operation............................................................................................................................ 540
13.4 Usage Notes ....................................................................................................................... 544
Section 14 Serial Communication Interface with FIFO (SCIF)
14.1 Overview............................................................................................................................ 547
14.2 Register Descriptions ......................................................................................................... 552
14.3 Operation............................................................................................................................ 580
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13.2.1 Watchdog Timer Counter (WTCNT).................................................................... 535
13.2.2 Watchdog Timer Control/Status Register (WTCSR) ........................................... 536
13.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 537
13.2.4 Notes on Register Access...................................................................................... 538
13.3.1 Operation in Watchdog Timer Mode.................................................................... 540
13.3.2 Operation in Interval Timer Mode........................................................................ 542
13.3.3 Operation when Standby Mode is Cleared ........................................................... 542
13.3.4 Timing of Overflow Flag (OVF) Setting.............................................................. 543
13.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting.............................. 543
13.4.1 Contention between WTCNT Write and Increment ............................................. 544
13.4.2 Changing CKS2 to CKS0 Bit Values ................................................................... 544
13.4.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 544
13.4.4 System Reset with WDTOVF .............................................................................. 545
13.4.5 Internal Reset in Watchdog Timer Mode.............................................................. 545
14.1.1 Features ................................................................................................................. 547
14.1.2 Block Diagrams .................................................................................................... 549
14.1.3 Pin Configuration.................................................................................................. 550
14.1.4 Register Configuration.......................................................................................... 551
14.2.1 Receive Shift Register (SCRSR) .......................................................................... 552
14.2.2 Receive FIFO Data Register (SCFRDR).............................................................. 552
14.2.3 Transmit Shift Register (SCTSR) ......................................................................... 553
14.2.4 Transmit FIFO Data Register (SCFTDR)............................................................. 553
14.2.5 Serial Mode Register (SCSMR)............................................................................ 553
14.2.6 Serial Control Register (SCSCR).......................................................................... 556
14.2.7 Serial Status 1 Register (SC1SSR)........................................................................ 560
14.2.8 Serial Status 2 Register (SC2SSR) ....................................................................... 565
14.2.9 Bit Rate Register (SCBRR) .................................................................................. 567
14.2.10 FIFO Control Register (SCFCR) .......................................................................... 575
14.2.11 FIFO Data Count Register (SCFDR).................................................................... 577
14.2.12 FIFO Error Register (SCFER) .............................................................................. 578
14.2.13 IrDA Mode Register (SCIMR) ............................................................................. 578
14.3.1 Overview............................................................................................................... 580
14.3.2 Operation in Asynchronous Mode........................................................................ 582
14.3.3 Multiprocessor Communication Function ............................................................ 594
14.3.4 Operation in Synchronous Mode .......................................................................... 602
............................. 547