HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 632

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

14.4
The SCIF has four interrupt sources: the break interrupt (BRI) request, receive-error interrupt
(ERI) request, receive-FIFO-data-full interrupt (RXI) request, and transmit-FIFO-data-empty
interrupt (TXI) request.
Table 14.13 shows the interrupt sources and their relative priorities. The interrupt sources can be
enabled or disabled with the TIE or RIE bit in SCSCR. Each kind of interrupt request is sent to the
interrupt controller independently.
When the TDFE flag is set to 1 in the serial status 1 register (SC1SSR), a TXI interrupt is
requested. A TXI interrupt request can activate the on-chip DMAC to perform data transfer. The
TDFE bit is cleared to 0 automatically when all writes to the transmit FIFO data register
(SCFTDR) by the DMAC are completed.
When the RDF flag is set to 1 in SC1SSR, an RXI interrupt is requested. An RXI interrupt request
can activate the on-chip DMAC to perform data transfer. The RDF bit is cleared to 0 automatically
when all receive FIFO data register (SCFRDR) reads by the DMAC are completed.
When the ER flag is set to 1, an ERI interrupt is requested. The on-chip DMAC cannot be
activated by an ERI interrupt request.
When the BRK flag is set to 1, a BRI interrupt is requested. The on-chip DMAC cannot be
activated by a BRI interrupt request.
A TXI interrupt indicates that transmit data can be written, and an RXI interrupt indicates that
there is receive data in SCFRDR. The TEI interrupt indicates that the transmit operation has
ended.
Table 14.13
Interrupt Source
ERI
RXI
BRI
TXI
SCIF Interrupt Sources and the DMAC
SCIF Interrupt Sources
Description
Receive error (ER)
Receive data full (RDF) or data ready (DR)
Break (BRK)
Transmit data FIFO empty (TDFE)
DMAC
Activation
Not possible
Possible
(RDF only)
Not possible
Possible
Priority on
Reset Release
High
Low
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