HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 240

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HD6417615

Manufacturer Part Number
HD6417615
Description
Hardware Manual
Manufacturer
Hitachi Semiconductor
Datasheet

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XYED and XYSD in BBRD as shown below. BDMRDH and BDMRDL are initialized to H'0000
by a power-on reset; after a manual reset, their values are undefined.
BDMRD Configuration
XYED = 0
XYED = 1
Bits 31 to 0:
BDMDn
0
1
Notes: 1. n = 31 to 0
222
2. When including the data bus value in the break condition, specify the operand size.
3. When specifying byte size, and using odd-address data as a break condition, set the
value in bits 7 to 0 of BDRD and BDMRD. When using even-address data as a break
condition, set the value in bits 15 to 8. The unused 8 bits of these registers have no
effect on the break condition.
Data
X data
(when XYSD = 0)
Y data
(when XYSD = 1)
Description
Channel D break data bit BDDn is included in break condition
Channel D break data bit BDDn is masked, and not included in condition
Upper 16 Bits
(BDMD31 to BDMD16)
Upper 16 bits maskable
Maskable
Lower 16 Bits
(BDMD15 to BDMD0)
Lower 16 bits maskable
Maskable
(Initial value)

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