HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 643

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

15.2.3
SITSR is a 16-bit register used to transmit serial data. The contents of this register are shifted in
MSB-first order in synchronization with the rising edge of the serial transmit clock (STCK), and
output from the STxD pin. The transfer data length is set by the transmit/receive data length select
bit (DL) in the serial control register (SICTR). When the DL bit is cleared to 0 (8-bit data length),
the lower 8 bits of SITDR are output. When the serial transmission synchronization signal (STS)
goes high, or the last data transmission ends without the synchronization enable (SE) bit being set
in SICTR, the contents of the transmit data register (SITDR) are transferred to SITSR, and if
TDRE is 0, TDRE is then set. If output of the next data begins before TDRE is cleared, an overrun
error occurs, the transmit overrun error flag (TERR) is set in SISTR, and a transmit overrun error
interrupt request is sent to the INTC.
15.2.4
SITDR is a 16-bit register that stores serial transmit data. Data should be written to SITDR when
the transmit data register empty flag (TDRE) is set to 1 in SISTR. If data is written to SITDR
when TDRE is 0, the previous data will be overwritten. When STS goes high or data output from
transmit shift register SITSR ends with the SE bit cleared to 0 in SICTR, the data in SITDR is
automatically transferred to SITSR, and if TDRE is 0, TDRE is then set. If the transmit interrupt
enable flag (TIE) is set, a transmit-data-empty interrupt (TDEI) request is sent to the INTC and
DMAC. When TIE is cleared, this interrupt request is not generated. When the DMAC writes to
SITDR, the TDRE flag is cleared automatically. The TDRE flag is set only by hardware. SITDR is
initialized to H'0000 by a reset.
630
Initial value:
Initial value:
Transmit Shift Register (SITSR)
Transmit Data Register (SITDR)
R/W:
R/W:
Bit:
Bit:
R/W
15
—
—
15
0
R/W
14
—
—
14
0
R/W
13
—
—
13
0
...
...
...
...
...
...
...
...
R/W
—
—
3
3
0
R/W
—
—
2
2
0
R/W
—
—
1
1
0
R/W
—
—
0
0
0