HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 437

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 20: TDE
0
1
Note: When transmission descriptor empty (TDE = 1) occurs, execute a software reset and initiate
Bit 19—Tx FIFO Underflow (TFUF): Indicates that underflow has occurred in the Tx FIFO
during frame transmission. Incomplete data is sent onto the line.
Bit 19: TFUF
0
1
Note: Whether E-DMAC operation continues or halts after underflow is controlled by the E-DMAC
Bit 18—Frame Received (FR): Indicates that a frame has been received and the receive descriptor
has been updated.
Note: The actual receive frame status is indicated in the receive status field in the descriptor.
Bit 18: FR
0
1
Bit 17—Rx Descriptor Exhausted (RDE): This bit is set if the receive active bit (RACT) setting is
“inactive” (RACT = 0) when the E-DMAC reads a receive descriptor.
Bit 17: RDE
0
1
Note: When receive descriptor empty (RDE = 1) occurs, receiving can be restarted by setting
Bit 16—Rx FIFO Overflow (RFOF): Indicates that the Rx FIFO has overflowed during frame
reception.
422
transmission. In this case, the address that is stored in the descriptor start address register
(TDLAR) is transmitted first.
operation control register (EDOCR).
RACT = 1 in the receive descriptor and initiating receiving.
Description
“1” transmit descriptor active bit (TACT) detected
“0” transmit descriptor active bit (TACT) detected (interrupt source)
Description
Underflow has not occurred
Underflow has occurred (interrupt source)
Description
Frame not received
Frame received (interrupt source)
Description
“1” receive descriptor active bit (RACT) detected
“0” receive descriptor active bit (RACT) detected (interrupt source)
(Initial value)
(Initial value)
(Initial value)
(Initial value)