HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 475

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

11.2.4
Note: Only 0 can be written, to clear the flag.
DMA channel control registers 0 and 1 (CHCR0 and CHCR1) are 32-bit read/write registers that
control the DMA transfer mode. They also indicate the DMA transfer status. Only the lower 16 of
the 32 bits are valid. They should be read and written as 32-bit values, including the upper 16 bits.
Write the initial values to the upper 16 bits. These bits always read 0. The registers are initialized
to H'00000000 by a reset and in standby mode. Values are retained during a module standby.
Bits 15 and 14—Destination Address Mode Bits 1, 0 (DM1, DM0): Select whether the DMA
destination address is incremented, decremented or left fixed (in single address mode, DM1 and
DM0 are ignored when transfers are made from a memory-mapped external device, or external
memory to an external device with DACK). DM1 and DM0 are initialized to 00 by a reset and in
standby mode. Values are retained during a module standby.
Bit 15: DM1
0
1
460
Initial value:
Initial value:
Initial value:
DMA Channel Control Registers 0 and 1 (CHCR0, CHCR1)
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit 14: DM0
0
1
0
1
DM1
R/W
R/W
AL
31
—
15
0
R
0
7
0
DM0
R/W
R/W
DS
30
—
14
0
R
0
6
0
Description
Fixed destination address
Destination address is incremented (+1 for byte transfer size,
+2 for word transfer size, +4 for longword transfer size, +16
for 16-byte transfer size)
Destination address is decremented (–1 for byte transfer size,
–2 for word transfer size, –4 for longword transfer size, –16
for 16-byte transfer size)
Reserved (setting prohibited)
SM1
R/W
R/W
DL
29
—
13
0
R
0
5
0
SM0
R/W
R/W
TB
…
…
…
…
12
0
4
0
TS1
R/W
R/W
TA
19
—
11
0
R
0
3
0
TS0
R/W
R/W
18
—
10
IE
0
R
0
2
0
R/(W)*
R/W
AR
TE
17
—
0
R
9
0
1
0
(Initial value)
R/W
R/W
AM
DE
16
—
0
R
8
0
0
0