HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 258

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Table 6.3
Branch
Delay
No delay
3. The location indicated by the address before branch occurrence, IA, differs according to the
240
If PID is an odd number, the value incremented by 2 indicates the instruction buffer, but the
equations in the table do not take this into account. Therefore, the calculation can be performed
using the values of BSA stored in BRSR and PID stored in BRFR.
kind of branch.
a. Branch instruction: Branch instruction address
b. Repeat loop: 2nd instruction from last in repeat loop
c. Interrupt: Instruction executed immediately before interrupt
In a repeat loop consisting of no more than three instructions, an instruction fetch cycle is not
generated. As the branch destination address is unknown, a PC trace cannot be performed.
Repeat_Start: inst (1);
Repeat End:
The address of the first instruction in the interrupt routine is stored in BRDR.
Figure 6.2 When Interrupt Occurs before Branch Instruction Is Executed
BSA Values Stored in Exception Handling before Execution of Branch
Destination Instruction
Branch Destination
(Dest)
4n
4n + 2
4n or 4n + 2
inst(2);
:
inst (n-1);
inst (n);
Exec:
Dest:
Int:
BSA
4n
4n + 2
4n
branch Dest
instr;
Interrupt
interrupt routine
BRDR
Branch Source Address Calculable by Means
of BRSR and BRFR
Exec = IA = BSA – 2
Dest = BSA
Exec = IA = BSA – 2
Address calculated from BRSR and BRFR
Not executed
PID
PID