HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 591

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

14.2.12 FIFO Error Register (SCFER)
The FIFO error register (SCFER) indicates the data location at which a parity error or framing
error occurred in receive data stored in the receive FIFO data register (SCFRDR).
SCFER can be read at all times.
Bits 15 to 0—Error Data Flags 15 to 0 (ED15 to ED0): These flags indicate the data location in the
receive FIFO data register at which an error occurred. When data in the nth stage of the buffer
contains an error, the nth bit is set to 1. Note that this register is not cleared by setting the RFRST
bit to 1 in SCFCR.
Bits 15 to 0:
ED15 to ED0
0
1
Note: A reset operation is performed in the event of a reset, when the module standby function is
14.2.13 IrDA Mode Register (SCIMR)
The IrDA mode register (SCIFMR) allows selection of the IrDA mode and the IrDA output pulse
width, and inversion of the IrDA receive data polarity.
SCIMR can be read and written to at all times.
SCIMR is initialized to H'00 by a reset, by the module standby function, and in standby mode.
578
Upper 8 bits:
Lower 8 bits:
Initial value:
Initial value:
used, or in standby mode. These flags are also cleared by reading the data in which the
parity error or framing error occurred from SCFRDR.
R/W:
R/W:
Description
No parity or framing error in data in corresponding stage of register FIFO
Parity or framing error present in data in corresponding stage of register FIFO
ED15
ED7
15
0
R
7
0
R
ED14
ED6
14
0
R
6
0
R
ED13
ED5
13
0
R
5
0
R
ED12
ED4
12
0
R
4
0
R
ED11
ED3
11
0
R
3
0
R
ED10
ED2
10
0
R
2
0
R
ED9
ED1
9
0
R
1
0
R
(Initial value)
ED8
ED0
8
0
R
0
0
R