HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 281

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

W31, W21, W11, W01
0
1
Bit 7: W31
0
1
W31, W21
0
1
264
When CS3 is DRAM, the number of CAS assert cycles is specified by wait control bits W31
and W30
When external wait mask bit A3WM in WCR2 is 0 and the number of CAS assert cycles is set
to 2 or more, external wait input is enabled.
When CS2 or CS3 is synchronous DRAM, CAS latency is specified by wait control bits W31
and W30, and W21 and W20, respectively
With synchronous DRAM, external wait input is ignored regardless of any setting.
Bit 6: W30
0
1
0
1
W30, W20
0
1
0
1
W30, W20, W10, W00
0
1
0
1
Description
1 cycle
2 cycles
3 cycles
Reserved (do not set)
Description
1 cycle
2 cycles
3 cycles
4 cycles
Description
External wait input disabled without wait
External wait input enabled with one wait
External wait input enabled with two waits
Complies with the long wait specification of
bus control register 1, 3 (BCR1, BCR3).
External wait input is enabled (Initial value)
(Initial value)