HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 8

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

5.5
5.6
5.7
Section 6
6.1
6.2
6.3
iv
5.4.2
Interrupt Response Time.................................................................................................... 190
Sampling of Pins IRL3 –IRL0 ........................................................................................... 192
Usage Notes ....................................................................................................................... 193
Overview............................................................................................................................ 197
6.1.1
6.1.2
6.1.3
Register Descriptions ......................................................................................................... 201
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10 Break Data Mask Register C (BDMRC) .............................................................. 213
6.2.11 Break Bus Cycle Register C (BBRC) ................................................................... 215
6.2.12 Break Execution Times Register C (BETRC) ...................................................... 216
6.2.13 Break Address Register D (BARD)...................................................................... 217
6.2.14 Break Address Mask Register D (BAMRD) ........................................................ 218
6.2.15 Break Data Register D (BDRD) ........................................................................... 220
6.2.16 Break Data Mask Register D (BDMRD).............................................................. 221
6.2.17 Break Bus Cycle Register D (BBRD) .................................................................. 223
6.2.18 Break Execution Times Register D (BETRD)...................................................... 224
6.2.19 Break Control Register (BRCR) ........................................................................... 225
6.2.20 Branch Flag Registers (BRFR) ............................................................................. 231
6.2.21 Branch Source Registers (BRSR) ......................................................................... 232
6.2.22 Branch Destination Registers (BRDR) ................................................................. 233
Operation............................................................................................................................ 234
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
Stack State after Interrupt Exception Handling .................................................... 190
User Break Controller (UBC)
Features ................................................................................................................. 197
Block Diagram...................................................................................................... 198
Register Configuration.......................................................................................... 199
Break Address Register A (BARA)...................................................................... 201
Break Address Mask Register A (BAMRA) ........................................................ 202
Break Bus Cycle Register A (BBRA) .................................................................. 203
Break Address Register B (BARB) ...................................................................... 205
Break Address Mask Register B (BAMRB)......................................................... 206
Break Bus Cycle Register B (BBRB) ................................................................... 207
Break Address Register C (BARC) ...................................................................... 209
Break Address Mask Register C (BAMRC)......................................................... 210
Break Data Register C (BDRC)............................................................................ 212
User Break Operation Sequence ........................................................................... 234
Instruction Fetch Cycle Break .............................................................................. 235
Data Access Cycle Break...................................................................................... 236
Saved Program Counter (PC) Value ..................................................................... 237
X Memory Bus or Y Memory Bus Cycle Break .................................................. 237
Sequential Break ................................................................................................... 238
PC Traces.............................................................................................................. 239
Examples of Use ................................................................................................... 241
Usage Notes .......................................................................................................... 246
...................................................................... 197