HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 334

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

7.5.10
To use synchronous DRAM, the mode must first be set after the power is turned on. To properly
initialize the synchronous DRAM, the synchronous DRAM mode register must be written to after
the registers of the bus state controller have first been set. The synchronous DRAM mode register
is set using a combination of the CS2 or CS3 signal and the RAS, CAS/OE, and RD/WR signals.
They fetch the value of the address signal at that time. If the value to be set is X, the bus state
controller operates by writing to address X + H'FFFF0000 or X + H'FFFF8000 from the CPU,
which allows the value X to be written to the synchronous DRAM mode register. Whether X +
H'FFFF0000 or X + H'FFFF8000 is used depends on the specifications of the synchronous
DRAM. Use a value in the range H'000 to H'FFF for X. Data is ignored at this time, but the mode
is written using word as the size.
Write any data in word size to the following addresses to select the burst read single write
supported by the chip, a CAS latency of 1 to 3, a sequential wrap type, and a burst length of 8 or 4
(depending on whether the width is 16 bits or 32 bits).
For 16 bits:
For 32 bits:
To set burst read, burst write, CAS latency 1 to 3, wrap-type sequential, and burst length 8 or 4
(depending on whether the width is 16 bits or 32 bits), arbitrary data is written to the following
addresses, using the word size.
16-bit width:
32-bit width:
Figure 7.32 shows the mode register setting timing.
Writing to address X + H'FFFF0000 or X + H'FFFF8000 first issues an all-bank precharge
command (PALL), then issues eight dummy auto-refresh commands (REF) required for the
synchronous DRAM power-on sequence. Lastly, a mode register write command (MRS) is issued.
Three idle cycles are inserted between the all-bank precharge command and the first auto-refresh
Burst Read/Single Write
Burst Read/Burst Write
Power-On Sequence
CAS latency 1
CAS latency 2
CAS latency 3
CAS latency 1
CAS latency 2
CAS latency 3
CAS latency 1
CAS latency 2
CAS latency 3
CAS latency 1
CAS latency 2
CAS latency 3
H'FFFF0426
H'FFFF0446
H'FFFF0466
H'FFFF0848
H'FFFF0888
H'FFFF08C8
H'FFFF0026
H'FFFF0046
H'FFFF0066
H'FFFF0048
H'FFFF0088
H'FFFF00C8
(H'FFFF8426)
(H'FFFF8446)
(H'FFFF8466)
(H'FFFF8848)
(H'FFFF8888)
(H'FFFF88C8)
(H'FFFF8026)
(H'FFFF8046)
(H'FFFF8066)
(H'FFFF8048)
(H'FFFF8088)
(H'FFFF80C8)
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