HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 284

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

7.2.6
Bits 15 and 14—Reserved bits: These bits are always read as 0. The write value should always be
0.
Bits 13 to 11—CS4 Address/CS4 to RD/WEn Assertion (A4SW2–A4SW0): These bits specify the
number of cycles from address/CS4 output to RD/WEn assertion for the CS4 space.
Bit 13: A4SW2
0
1
Bit 10—Reserved bit: This bit is always read as 0. The write value should always be 0.
Bits 9 and 8—Area 4 RD/WEn Negation to Address/CS4 Hold (A4HW1, A4HW0): These bits
specify the number of cycles from RD/WEn negation to address/CS4 hold for the CS4 space.
Bit 9: A4HW1
0
1
Initial value:
Initial value:
Wait Control Register 3 (WCR3)
R/W:
R/W:
Bit:
Bit:
Bit 12: A4SW1
0
1
0
1
Bit 8: A4HW0
0
1
0
1
A3SHW1 A3SHW0 A2SHW1 A2SHW0 A1SHW1 A1SHW0 A0SHW1 A0SHW0
R/W
15
—
0
R
7
0
R/W
14
—
0
R
6
0
Bit 11: A4SW0
0
1
0
1
0
1
0
1
Description
0.5 cycle, CS4 hold cycle = 0 cycles
1.5 cycle, CS4 hold cycle = 1 cycle
3.5 cycle, CS4 hold cycle = 3 cycles
5.5 cycle, CS4 hold cycle = 5 cycles
A4SW2
R/W
R/W
13
0
5
0
A4SW1 A4SW0
R/W
R/W
12
0
4
0
Description
0.5 cycles
1.5 cycle
3.5 cycles
5.5 cycles
7.5 cycles
Reserved (do not set)
Reserved (do not set)
Reserved (do not set)
R/W
R/W
11
0
3
0
R/W
10
—
0
R
2
0
A4HW1 A4HW0
R/W
R/W
9
0
1
0
(Initial value)
(Initial value)
R/W
R/W
8
0
0
0
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