HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 510

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

When external memory is set as bank active synchronous DRAM, during a write the acknowledge
signal is output across the wait and column address when the row address is the same as the
previous address output (figure 11.26). When the row address is different from the previous
address, the acknowledge signal is output across the precharge, row address, wait and column
address (figure 11.27).
(Active high)
Figure 11.26 DACKn Output in Synchronous DRAM Write
Figure 11.27 DACKn Output in Synchronous DRAM Write
Address
DACKn
Clock
bus
(Bank Active, Different Row Address, AM = 1)
(Active high)
(Bank Active, Same Row Address, AM = 1)
Address
DACKn
Clock
bus
Precharge
(basic timing)
DMAC write
(basic timing)
DMAC write
address
Column
address
Row
address
Column
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