HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 622

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

1. The SCIF performs internal initialization in synchronization with serial clock input or output.
2. The received data is stored in the receive shift register (SCRSR) in LSB-to-MSB order or
3. If the RIE bit setting in the serial control register (SCSCR) is 1 when the RDF flag is set to 1, a
In serial reception, the SCIF operates as described below.
MSB-to-LSB order according to the setting of the RLM bit in SC2SSR.
After reception, the SCIF checks whether the receive data can be transferred from SCRSR to
the receive FIFO data register (SCFRDR). If this check is passed, the receive data is stored in
SCFRDR.
If a receive error is detected in the error check, the operation is as shown in table 14.11.
Neither transmit nor receive operations can be performed subsequently when a receive error
has been found in the error check.
Also, as the RDF flag is not set to 1 when receiving, the flag must be cleared to 0.
receive-FIFO-data-full interrupt (RXI) is requested. If the RIE bit setting in SCRSR is 1 when
the ORER flag is set to 1, a receive-error interrupt (ERI) is requested.
Figure 14.21 shows an example of SCIF operation in reception.
Figure 14.20 Sample Serial Reception Flowchart (2)
No
Clear ORER flag to 0 in SC2SSR
Overrun error handling
Error handling
ORER = 1?
End
Yes
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