HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 249

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

6.2.20
The branch flag registers (BRFR) comprise a set of four 16-bit read-only registers. The BRFR
registers contain flags indicating whether the actual branch addresses (in a branch instruction,
repeat, interrupt, etc.) have been saved in BRSR and BRDR, and a 3-bit pointer indicating the
number of cycles from fetch to execution of the last instruction executed. The BRFR registers
form a FIFO (first-in first-out) queue for PC trace use. The queue is shifted at each branch.
Bits SVF and DVF are initialized by a power-on reset, but bits PID2 to PID0 are not.
Bit 15—Source Verify Flag (SVF): Indicates whether the address and pointer that enable the
branch source address to be calculated have been stored in BRSR. This flag is set when the
instruction at the branch destination address is fetched, and reset when BRSR is read.
Bit 15: SVF
0
1
Bits 14 to 12—PID2 to PID0: These bits comprise a pointer that indicates the instruction buffer
number of the instruction executed immediately before a branch occurred.
Bits 14 to 12:
PID2 to PID0
0
1
Bit 7—Destination Verify Flag (DVF): Indicates whether the branch source address has been
stored in BRDR. This flag is set when the instruction at the branch destination address is fetched,
and reset when BRDR is read.
Initial value:
Initial value:
R/W:
R/W:
Branch Flag Registers (BRFR)
Bit:
Bit:
SVF
DVF
15
0
R
7
0
R
Description
BRSR value is invalid
BRSR value is valid
Description
PID indicates instruction buffer number
PID+2 indicates instruction buffer number
Undefined Undefined Undefined
PID2
14
—
R
6
0
R
PID1
13
—
R
5
0
R
PID0
12
—
R
4
0
R
11
—
—
0
R
3
0
R
10
—
—
0
R
2
0
R
—
—
9
0
R
1
0
R
(Initial value)
(Initial value)
—
—
8
0
R
0
0
R
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