HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 588

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

14.2.10 FIFO Control Register (SCFCR)
The FIFO control register (SCFCR) performs data count resetting and trigger data number setting
for the transmit and receive FIFO registers, and also contains a loopback test enable bit.
SCFCR can be read or written to at all times.
SCFCR is initialized to H'00 by a reset, by the module standby function, and in standby mode.
Bits 7 and 6—Receive FIFO Data Number Trigger (RTRG1, RTRG0): These bits are used to set
the number of receive data bytes that sets the receive data full (RDF) flag in the serial status 1
register (SC1SSR).
The RDF flag is set when the number of receive data bytes in the receive FIFO data register
(SCFRDR) is equal to or greater than the trigger set number shown in the following table.
Bit 7: RTRG1
0
1
Note: * Initial value
Bits 5 and 4—Transmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used to set
the number of remaining transmit data bytes that sets the transmit FIFO data register empty
(TDFE) flag in the serial status 1 register (SC1SSR).
The TDFE flag is set when the number of transmit data bytes in the transmit FIFO data register
(SCFTDR) is equal to or less than the trigger set number shown in the following table.
Initial value:
R/W:
Bit:
RTRG1
Bit 6: RTRG0
0
1
0
1
R/W
7
0
RTRG0
R/W
6
0
TTRG1
Receive Trigger Number
1*
4
8
14
R/W
5
0
TTRG0
R/W
4
0
MCE
R/W
3
0
TFRST
R/W
2
0
RFRST
R/W
1
0
LOOP
R/W
0
0
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