HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 242

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

6.2.18
When a channel D execution-times break condition is enabled (by setting the ETBED bit in
BRCR), this 16-bit register specifies the number of times a channel D break condition occurs
before a user break interrupt is requested. The maximum value is 2
channel D break condition occurs, the value in BETRD is decremented by 1. After the BETRD
value reaches H'0001, an interrupt is requested when a break condition next occurs.
As exceptions and interrupts cannot be accepted for instructions in a repeat loop comprising no
more than three instructions, BETRD is not decremented by the occurrence of a break condition
for an instruction in such a repeat loop (see 4.6, When Exception Sources Are Not Accepted).
Bits 15 to 12 are always read as 0, and should only be written with 0.
BETRD is initialized to H'0000 by a power-on reset.
224
Initial value:
Initial value:
Break Execution Times Register D (BETRD)
R/W:
R/W:
Bit:
Bit:
ETRD7
R/W
15
—
0
R
7
0
ETRD6
R/W
14
—
0
R
6
0
ETRD5
R/W
13
—
0
R
5
0
ETRD4
R/W
12
—
0
R
4
0
ETRD11 ETRD10 ETRD9
ETRD3
R/W
R/W
11
0
3
0
12
– 1 times. Each time a
ETRD2
R/W
R/W
10
0
2
0
ETRD1
R/W
R/W
9
0
1
0
ETRD8
ETRD0
R/W
R/W
8
0
0
0