HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 254

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

6.3.3
1. Memory cycles for which a CPU data access break can be set are memory cycles due to
2. Table 6.2 shows the bits of the break address register and the address bus that are compared for
Table 6.2
Access Size
Longword
Word
Byte
3. When data value is included in break condition in channel C
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instructions and stack operations and vector reads when exception handling is executed. A
CPU data access break cannot be set for a vector fetch cycle of an external vector interrupt, for
burst write of a synchronous DRAM, or for a dammy access cycle of a single read.
each operand size to determine whether a break condition has been matched.
This means, for example, that if address H'00001003 is set without specifying a size condition,
bus cycles that satisfy the break conditions are as follows (assuming that all other conditions
are satisfied):
Longword access at address H'00001000
Word access at address H'00001002
Byte access at address H'00001003
When the data value is included in the break conditions, specify longword, word, or byte as the
operand size in break bus cycle register C (BBRC). When the data value is included in the
break conditions, a break interrupt is generated on a match of the address condition and the
data condition.
When byte data is specified, set the same data in the two bytes comprising bits 15 to 8 and bits
7 to 0 in break data register C (BDRC) and break data mask register C (BDMRC). If word or
byte is designated, bits 31 to 16 of BDRC and BDMRC are ignored.
Similar conditions apply when the data value is included in the break conditions for channel D.
Data Access Cycle Break
Data Access Cycle Address and Operand Size Comparison Conditions
Compared Address Bits
Bits 31 to 2 of break address register compared with bits 31 to 2 of address
bus
Bits 31 to 1 of break address register compared with bits 31 to 1 of address
bus
Bits 31 to 0 of break address register compared with bits 31 to 0 of address
bus