HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 350

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

7.6.8
The bus state controller includes a function for controlling DRAM refreshing. Distributed
refreshing using a CAS-before-RAS refresh cycle can be performed by clearing the RMODE bit to
0 and setting the RFSH bit to 1 in MCR. Consecutive refreshes can be generated by setting bits
RRC2–RRC0 in RTCSR. If DRAM is not accessed for a long period, self-refresh mode, which
uses little power consumption for data retention, can be activated by setting both the RMODE and
RFSH bits to 1.
CAS-Before-RAS Refreshing: Refreshing is performed at intervals determined by the input clock
selected by bits CKS2–CKS0 in RTCSR, and the value set in RTCOR. The RTCOR value and the
value of bits CKS2–CKS0 in RTCSR should be set so as to satisfy the refresh interval
specification for the DRAM used. First make the settings for RTCOR, RTCNT, and the RMODE
and RFSH bits in MCR, then make the CKS2–CKS0 and RRC2–RRC0 settings in RTCSR. When
Note: * DACKn waveform when active-low is specified
Refreshing
Figure 7.47 DMA Single Transfer Mode Write Cycle Timing
CKIO
A24–A16
A15–A1
RAS
CASn
RD/WR
D31–D0
DACKn *
(RAS Down Mode, Same Row Address)
Tdsww
Low level
Tc1
Tc2
333