DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 614

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 ROM
18.7.1
Program Mode
When writing data or programs to flash memory, the program/program-verify flowchart shown in
figure 18.12 should be followed. Performing program operations according to this flowchart will
enable data or programs to be written to flash memory without subjecting the device to voltage
stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a
time.
The wait times after bits are set or cleared in the flash memory control register (FLMCR1,
FLMCR2) and the maximum number of programming operations (N) are shown in table 21.10 in
section 21.2.5, Flash Memory Characteristics.
Following the elapse of (tsswe) µs or more after the SWE1 and SWE2 bits are set to 1 in FLMCR1
and FLMCR2, 128-byte data is written consecutively to the write addresses. The lower 8 bits of
the first address written to must be H'00 and H'80, 128 consecutive byte data transfers are
performed. The program address and program data are latched in the flash memory. A 128-byte
data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must
be written to the extra addresses.
Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
Set a value greater than (tspsu + tsp + tcp + tcpsu) µs as the WDT overflow period. Preparation
for entering program mode (program setup) is performed next by setting the PSU1 and PSU2 bits
in FLMCR1 and FLMCR2. The operating mode is then switched to program mode by setting the
P1 and P2 bits in FLMCR1 and FLMCR2 after the elapse of at least (tspsu) µs. The time during
which the P1 and P2 bits are set is the flash memory programming time. Make a program setting
so that the time for one programming operation is within the range of (tsp) µs.
The wait time after P1 and P2 bits setting must be changed according to the number of
reprogramming loops. For details, see section 21.2.5, Flash Memory Characteristics.
Rev. 3.00 Mar 21, 2006 page 584 of 814
REJ09B0302-0300