DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 74

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 2 CPU
Explanation of BCLR Instruction
To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write-
only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to DDR to complete the BCLR instruction.
As a result, P4
are set to 1, making P4
The BCLR instruction can be used to clear flags in the internal I/O registers to 0. In an interrupt-
handling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the
flag ahead of time.
2.7
2.7.1
The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except program-
counter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,
BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit
number in the operand.
Table 2.11 Addressing Modes
No.
1
2
3
4
5
6
7
8
Rev. 3.00 Mar 21, 2006 page 44 of 814
REJ09B0302-0300
Addressing Modes
Addressing Mode
Register direct
Register indirect
Register indirect with displacement
Register indirect with post-increment
Register indirect with pre-decrement
Absolute address
Immediate
Program-counter relative
Memory indirect
Addressing Modes and Effective Address Calculation
0
DDR is cleared to 0, making P4
7
and P4
6
output pins.
0
an input pin. In addition, P4
Symbol
@ERn
@(d:16, ERn)/@(d:24, ERn)
@ERn+
@–ERn
@aa:8/@aa:16/@aa:24
#xx:8/#xx:16/#xx:32
@(d:8, PC)/@(d:16, PC)
@@aa:8
Rn
7
DDR and P4
6
DDR