DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 601

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.5.3
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode,
when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the
SWE1 bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be
erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can
be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be
automatically cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and
writes are invalid.
The flash memory block configuration is shown in table 18.3.
18.5.4
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode,
when a low level is input to the FWE pin. Bits EB11 to EB8 will be initialized to 0 if bit SWE1 of
FLMCR1 is not set, even though a high level is input to pin FWE. Also, bits EB15 to EB12 will be
initialized to 0 if bit SWE2 of FLMCR2 is not set. When a bit in EBR2 is set to 1, the
corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1
and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both
EBR1 and EBR2 to be automatically cleared to 0. When on-chip flash memory is disabled, a read
will return H'00, and writes are invalid.
The flash memory block configuration is shown in table 18.3.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Erase Block Register 1 (EBR1)
Erase Block Register 2 (EBR2)
EB15
R/W
R/W
EB7
7
0
7
0
EB14
R/W
R/W
EB6
6
0
6
0
EB13
R/W
R/W
EB5
5
0
5
0
EB12
R/W
R/W
EB4
4
0
4
0
Rev. 3.00 Mar 21, 2006 page 571 of 814
EB11
R/W
R/W
EB3
3
0
3
0
EB10
R/W
R/W
EB2
2
0
2
0
REJ09B0302-0300
R/W
EB9
R/W
EB1
Section 18 ROM
1
0
1
0
R/W
R/W
EB0
EB8
0
0
0
0