DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 654

MCU 5V 512K 100-TQFP

DF3052BX25V

Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3052BX25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 20 Power-Down State
20.4
20.4.1
To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in
SYSCR.
In software standby mode, current dissipation is reduced to an extremely low level because the
CPU, clock, and on-chip supporting modules all halt. The DMAC and on-chip supporting modules
are reset. As long as the specified voltage is supplied, however, CPU register contents and on-chip
RAM data are retained. The settings of the I/O ports and refresh controller* are also held.
Note: * RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their
20.4.2
Software standby mode can be exited by input of an external interrupt at the NMI, IRQ
IRQ
Exit by Interrupt: When an NMI, IRQ
clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0
in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and
interrupt exception handling begins. Software standby mode is not exited if the interrupt enable
bits of interrupts IRQ
CPU.
Exit by RES
supplied immediately to the entire chip. The RES signal must be held low long enough for the
clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling.
Exit by STBY
Rev. 3.00 Mar 21, 2006 page 624 of 814
REJ09B0302-0300
2
pin, or by input at the RES or STBY pin.
previous states.
RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are
RES
STBY Input: Low input at the STBY pin causes a transition to hardware standby mode.
STBY
RES
STBY
Transition to Software Standby Mode
Exit from Software Standby Mode
Software Standby Mode
0
, IRQ
1
, and IRQ
2
0
are cleared to 0, or if these interrupts are masked in the
, IRQ
1
, or IRQ
2
interrupt request signal is received, the
0
, IRQ
1
, or

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