DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 27

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.1 Features ............................................................................................................................. 555
18.2 Overview........................................................................................................................... 556
18.3 Pin Configuration.............................................................................................................. 564
18.4 Register Configuration ...................................................................................................... 564
18.5 Register Descriptions ........................................................................................................ 565
18.6 On-Board Programming Modes ........................................................................................ 574
18.7 Programming/Erasing Flash Memory ............................................................................... 582
18.8 Protection .......................................................................................................................... 591
18.9 Flash Memory Emulation in RAM.................................................................................... 597
18.10 Flash Memory PROM Mode............................................................................................. 599
18.11 Notes on Flash Memory Programming/Erasing................................................................ 601
Section 19 Clock Pulse Generator
19.1 Overview........................................................................................................................... 607
19.2 Oscillator Circuit............................................................................................................... 609
18.2.1 Block Diagram ..................................................................................................... 556
18.2.2 Mode Transitions ................................................................................................. 556
18.2.3 On-Board Programming Modes........................................................................... 559
18.2.4 Flash Memory Emulation in RAM ...................................................................... 561
18.2.5 Differences between Boot Mode and User Program Mode ................................. 562
18.2.6 Block Configuration............................................................................................. 563
18.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 565
18.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 568
18.5.3 Erase Block Register 1 (EBR1) ........................................................................... 571
18.5.4 Erase Block Register 2 (EBR2) ........................................................................... 571
18.5.5 RAM Control Register (RAMCR) ....................................................................... 572
18.6.1 Boot Mode ........................................................................................................... 574
18.6.2 User Program Mode............................................................................................. 580
18.7.1 Program Mode ..................................................................................................... 584
18.7.2 Program-Verify Mode.......................................................................................... 585
18.7.3 Notes on Program/Program-Verify Procedure..................................................... 585
18.7.4 Erase Mode .......................................................................................................... 589
18.7.5 Erase-Verify Mode............................................................................................... 589
18.8.1 Hardware Protection ............................................................................................ 591
18.8.2 Software Protection.............................................................................................. 593
18.8.3 Error Protection.................................................................................................... 594
18.8.4 NMI Input Disable Conditions............................................................................. 595
18.10.1 Socket Adapters and Memory Map...................................................................... 599
18.10.2 Notes on Use of PROM Mode ............................................................................. 600
19.1.1 Block Diagram ..................................................................................................... 608
.................................................................................. 607
Rev. 3.00 Mar 21, 2006 page xxv of xxviii